Subsircuit analisys, converting subcircuit netlist to schematic

SPICE & LTSPICE, Subcircuits

Imagine, you are lucky to get subcircuit for component you’d like to simulate. How good this subcircuit is?

Quality of simulation strongly depends on quality of subcircuit model that is used. Unfortunately, netlist for complicated subcircuit does not look like schematic drawing and is hard to interpret. Yes, everything is there, but as many design engineers, I’m thinking in terms of schematic when it is comes to necessity of interpreting functional behavior. This means that next step for me would be converting subsircuit netlist to schematic.

I will use LTSPICE editor to draw schematic. The most convenient setup for me would be opening 2 windows, one with library file containing subcircuit definition and the other window, where I will draw schematic, based on this definition.

This time we will try to convert and analyze popular linear regulator LM317. I was not lucky enough to get subcicuit of this part from any vendors, who manufacture this part, so I Googled it and was able to get one model LM317/TI from one of EE forums and a couple of very similar models from Yahoo LTSPICE group repository. I put them all into LM317.lib and will use as an example.

I will not try to draw complete schematic in one iteration. It is very unlikely to group and place components from complicated subcircuit in a readable schematic just at the beginning. Instead, I will enter drawings of components as they appear on subcircuit netlist one by one, keeping some place for wires. I will also connect short wires to every pin of component and mark the net names the same way they are marked in the netlist. I will not connect different parts together in this preliminary step. To finalize this first step, I will enter values for some of components. I’m usually entering values for most passive components because it helps understanding circuit functionality. The way how it looks like at the end of preliminary stage is reflected in the picture and LM317_1.asy schematic.

 

Next step is to group together parts that represent functional blocks and closely related to each other. This may be complicated and may require a couple of iterations. Netnames, marked in the previous stage are visible on schematic and netnames help to group related components together. Look at LM317_2.asy schematic, representing this stage of evaluation.

 

The last step is to finalize placement and make connections. Updated schematic is LM317_3.asy.

 

After this step I’m usually evaluating functionality of schematic that I’m getting. LM317_3.asy is looking reasonable except emitters of Q6 and Q9, going nowhere. There were a couple of commented lines in LM317/TI model and after analyzing models from different vendors, I made corrections to schematic and saved it as LM317_4.asy. We are almost done with our conversion from subcircuit to schematic.

If the plan is to get just schematic equivalent of subcircuit and not use it for simulation-we can stop here. However, sometimes it is helpful to make schematic that would be possible to analyze, evaluating performance of internal components and probing some internal points. It is possible to modify subcircuit itself to provide this probing capability. But we have schematic almost ready and I will modify it to provide simulation capability. To do so, it is necessary to assign values and parameters to all components and include all model statements, representing used models, to schematic. This is also helpful for checking quality of your subcircuit to schematic conversion.

In this example, you have to change properties of semiconductor devices to represent proper models. Just hold control button and right click on the part to open component attribute editor and change corresponding fields. For example, for Q8 you have to change Value from PNP to QPL. As soon as area parameter 0.2 is used in subcircuit description of Q8, you should also add area=0.2 to Value2 field.

 

Then I’ll create schematic symbol to represent hierarchical block as described in Hierarchical Blocks in LTSPICE and create a test bench to try and verify how my conversion works.

Building test bench circuit is essential step. In this example, I made a couple of errors, while converting subcircuit to schematic. LM317_4.asy picture shows one of them.

Very helpful way of looking for possible error would be generating netlist for your schematic. Select View –> SPICE Netlist. It should look very similar to original subcircuit netlist, including all necessary models and values.

There are some differences between results for subcircuit and my converted schematic. Test-bench shows slightly different output voltage and so far, I was not able to locate the root cause for this difference

Files used in examples are included in LM317SC

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